IBIS Macromodel Task Group

Meeting date: 29 October 2013

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                       David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
                            * Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
                              Hassan Rafat
                              Ron Olisar
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                  James Zhou
SiSoft:                     * Walter Katz
                            * Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

The meeting was led by Arpad Muranyi

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Opens:

- Arpad showed a list of dates to schedule our meetings
  - Mike can not meet Nov 26
  - Arpad can not meet Nov 19 & 26
  - We decided to cancel for Dec 24 & 31

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Call for patent disclosure:

- None

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Review of ARs:

- Walter create more EMD-like examples by request
  - Walter: Answers to some questions are needed

- Brad check on JEITA LPB information from Cadence Japan
  - No report

- Arpad call for email vote on 7 questions
  - Done

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New Discussion:

JEITA LPB:
- MM: They have a PAR P2401 group to form a standard
  - The question is how how much that overlaps with our work
- Walter: WIll they meet at the plenary meeting in Dallas in November?
- MM: Unlikely
- Arpad: JEITA officials tend to be difficult to contact
- MM: It may report into DASC, which might help us get regular updates.
- Brad: Cadence Japan require review of anything disclosed
  - I have information not yet looked at, not sure what can be shared.
- MM: Some information was publicly displayed at DAC
- Brad: That was not very informative
- Arpad: This will not stay on the agenda, it can be an open

Vote:
- Walter clarified different scenrios from the survey questions
- Fangyi: How does one pin connect to multiple pads?
  - Does each die receive the same data?
- Walter: The chip selects control which one acts
  - Stacked memories are delivered as a single chip
- Arpad: #1 is a special case of #2
  - In #2 there can be pad to pad connections
- Walter: And in #1 the die are all the same
- Randy: If a package has a DRAM and a NAND Flash the models should not go into the same file
- Arpad: EBD can call those by reference
- John: This almost allows multiple buffers behind one pad
  - That can be done within the existing [Component]
  - This is independent of #1 and #2
- Walter: We should be looking at problems for now, not solutions
- John: #2 and #5 overlap somewhat
- Walter: The difference is whether they are on different dice
  - The question is if we want to require EMD for any of this
- Arpad: IBIS could be just for the die, and EBD would take care of everything else
- Walter: That would be a new kind of IBIS component
  - The package owuld include on-die interconnect
- Walter: On-die is fundamentally different
- Arpad: The existing keyword would not be used
- Walter: We need hierarchy
- John: The ability to bring in different chip types might help

Mike relayed vote counts from 4 survey responses
Walter recorded them on-screen
- Walter: Some votes should be considered exceptions, requiring EMD

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
